Fault Coverage Testing on the ISCAS’89 S1423 Sequential Circuit using Scan Based Design and Synopsis Tetramax

Wirmanto Suteddy, Anugrah Adiwilaga, Dastin Aryo Atmanto


We tested the ISCAS'89 S1423 series with a scan design method, both non-scan, full-scan, and partial-scan, but for the partial-scan, the method we propose uses a structured random approach. The purpose of this study is to determine the evaluation and performance with the best computational time with the proposed method to produce high fault coverage results. Testing the ISCAS'89 S1423 circuit in the form of verilog was carried out using tetramax synopsis, the partial-scan test requires a strategy in determining the flip flop to be used as a scannable flip flop, the test results using the full scan method produce 100% test coverage and fault coverage, but this method provides gate overhead loss of 24.06% and slower chip performance. To reduce the gate overhead loss, a partial-scan method will be applied with the approach of choosing from 74 DFF which will be used as scannable flip flops, the test with the best results we did through the 37 DFF approach with the highest input obtained test coverage of 98.17% and fault coverage 96.76% with 171.11 CPU Time with gate overhead reduced by 12.03%. The next approach with the best results with the approach of 50 DFF highest output plus DFF which is not self-loop obtained test coverage of 99.24% and fault coverage of 98.47% with gate overhead successfully reduced by 16.26% with CPU Time 43.39

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